Fast switching of information, be it samples of analog signals or alphanumeric data, is an important task in a communication network. The network nodes, in which lines or transmission links from various directions are interconnected for exchanging information between them, are often the cause of delay in the transmission. If much traffic is concentrated in a node, and particularly if most of the traffic passes through only few of the links, increased delays or even loss of information can often be encountered. It is therefore desirable to have switching nodes which allow fast routing.
In European patent application 312628 a switching apparatus is described for interconnecting a plurality of incoming and outgoing transmission links of a communication network, or for exchanging data between incoming and outgoing computer and workstation connection links. Furthermore, known packet formats are described.
An overview of prior art switching technology is given on the Internet page www.zurich.ibm.com/Technology/ATM/SWOCPWP, wherein an introduction into the PRIZMA Chip is illustrated. Another source for information about this topic is the publication “A flexible shared-buffer switch for ATM at Gbit/s rates” by W. E. Denzel, A. P. J. Engbersen, and I. Iliadis, which is published in “Computer Networks and ISDN Systems,” (0169-7552/94), Elsevier Science B.V., Vol. 27, No. 4, pp. 611–624.
The PRIZMA chip comprises a shared common output buffer and has 16 input ports and 16 output ports which provide a port speed of 300–400 Mbit/s. The switch's principle is first to route incoming packets through a fully parallel I/O routing tree and then to queue the routed packets in the output buffer. In addition to this, the chip uses a separation between data (payload) and control (header) flow. Only the payloads are stored in a dynamically shared output buffering storage. The PRIZMA chip has a scaleable architecture and hence offers multiple expansion capabilities with which the port speed, the number of ports and the data throughput can be increased. These expansions can be realized based on a modular use of the PRIZMA. Also single-stage or multi-stage switch fabrics can be constructed in a modular way.
The PRIZMA chip is especially suited for broadband telecommunications, based on ATM, i.e. the Asynchronous Transfer Mode. However, the concept is not restricted to ATM-oriented architectural environments. ATM is based on short, fixed-length packets, often called cells, and is supposed to be applied as the integrated switching and transmission standard for the future public Broadband Integrated Services Digital Network (BISDN). PRIZMA's topology and queuing arrangement for contention resolution with a high degree of parallelism. The routing function is performed in a distributed way at the hardware level, referred to as self-routing. ATM packets are classified into several packet types, particularly packet types with different payload sizes, and the PRIZMA chip is dedicated to handling packets with a payload up to 64 bytes. However, also packet payloads with 12, 16, 32 or 48 bytes are often to be transported.
In the case of multiple data sources being connected to a single switching device, each of the sources is assigned a specific bandwidth which may not be or may only negligibly be exceeded, otherwise the performance of the switching device would decrease, thereby introducing bigger latency or even data loss. Data sources, respectively the companies that provide the data, are subjected to a bandwidth usage policy which typically leads to penalty fees, if a company exceeds its assigned bandwidth level. It is the task of the switching device to treat the data sources fairly in processing the data packets from those data sources that stay below the assigned bandwidth and to, if necessary, only decrease processing quality to those data packets that arrive in excess to the assigned bandwidth. This so-called “quality of service” is crucial in order to satisfy the interests of customers who have obtained the right to be treated fair concerning their data packets. Unfair treatment can lead to customer dissatisfaction and financial losses. For regulating the incoming flow of data packets to a switching device, in U.S. Pat. No. 5,493,566 a system is described for controlling the flow of data cells through a packet switch which combines both input and output buffers in a feedback loop. The fullness level of the output buffers is continuously monitored and reported to an access device on the input side of the switch. The access device includes input buffers and a throttling device to stop the flow of data cells, and to hold them in the input buffers, when the fullness level of the output buffers exceeds a predetermined level. A status message of output buffer fullness is compared to an access message indicating which output buffers are addressed by cells in the input buffers and only those cells addressed to overfull output buffers are stopped by the throttling device.
The throttling device according to the latter-mentioned prior art is the part of the switch adapter regulating the speed of the data packets being sent to the switching device. At the switching device itself there is no mechanism to cope with an adapter which is not throttling the data packet stream according to the reported output buffer status, due to whatever reason.
It is, therefore, an object of the invention to provide a switching device and method which is able to cope with switch adapters, that continue to send data packets despite backpressure, in order to be able to offer fair treatment and quality of service to all connected data sources.